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Verilog_Development_Board_Sources
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
changyongdevhdl
- 4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态 机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the cases of design, the highest
sdgshjd
- 数字系统设计这是有关的相关源代码,有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器(三种不同的描述方式) 加法器描述 8位总线收发器:74245 (注2) 地址译码(for m68008) 多路选择器(使 BR> ... -Digital System Design This is the underlying source code, a simple C
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器,乘法器,除法器,多路选择器,二进制转BCD码,加法器,减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-p
用assign 语句描述的三态门
- 用assign 语句描述的三态门,三态双向驱动器,3-8 译码器,8-3 优先编码器等等,With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
vhdl
- 3vhdl简单程序设计;4,8-3优先编码器5,3-8译码器;6,6d锁存器;7,数码管扫描显示;8,四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
encode
- 8位优先编码器。 8位优先编码器。-8-bit priority encoder. 8-bit priority encoder. 8-bit priority encoder.
Dualpriorityencoder
- 用VHDL编译的源代码,两位优先级编码器,输入一个十进制数,直接显示头两个‘1’所在的位,解压后直接用Quartus打开project即可-Compiled with VHDL source code, the two priority encoder, enter a decimal number, direct show
decoder_3_8
- 采用VHDL语言编写8线-3线优先编码器,在MAX+plus软件下实现。-Using VHDL language-3 line 8 line priority encoder, in MAX+ Plus software to achieve.
fangzhen
- 基于Matlab下的Simulink模块对74LS148优先编码器的仿真-Simulink under Matlab-based module 74LS148 priority encoder simulation
2
- 里面有四个vhdl源程序 分别为状态机 三位表决器 和交通灯 优先编码器-There are four VHDL source code for the state machine, respectively, the three voting machines and traffic lights priority encoder
Digital_Responder(Digital_Circuit)
- 数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出;用控制电路和主持人开关启动报警电路,以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能,构成扩展电路。经过布线、焊接、调试等工作后数字抢答器成形。-Answer the number is controlled by the main circuit and the expansion of circuit components. Priority enco
priority
- 这是自己编写的一个优先编码器程序,很简单,希望大家不要见笑-This is a priority for the preparation of their own encoder procedure, very simple, hope that we will not stock
vhdlexperiences
- 计数器、频率计、优先编码器、数码管扫描电路、数据选择器-Counter, frequency meter, priority encoder, digital tube scanning circuits, data selector
szqdq
- 数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出;用控制电路和主持人开关启动报警电路,以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能,构成扩展电路。经过布线、焊接、调试等工作后数字抢答器成形。-Answer the number of circuits is controlled by the main circuit and expansion. Priority encoder circuit, l
shuziqiangdaqi123
- 数字抢答器(数字电路)【课程设计】数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出;用控制电路和主持人开关启动报警电路,以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能,构成扩展电路。经过布线、焊接、调试等工作后数字抢答器成形。-Answer the number of devices (digital circuit) curriculum design】 【Answer is controlled b
Mars-EP1C6-F_code1
- 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit priority encoder, multipliers, mul
8code
- 这是cpld,epm240与优先编码器的程序,希望与大家分享-This is cpld, epm240 with the priority encoder program, hopes to share with you
irq_decoder
- 中断优先编码器的描述,输出中断向量供CPU读取,非常好用,只要稍稍修改,就可以产生您所需要的中断向量。-Descr iption of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need.
6_coder
- VHDL编写!8-3线编码器大全! 包括 coder8_3.vhd 8线/3线编码器 coder8_3_1.vhd 8线/3线编码器 sn74ls148.vhd 8线/3线优先编码器 coder16_4.vhd 16线/4线优先编码器-VHDL write! 8-3 line encoder Daquan! Including coder8_3.vhd 8 line/3 line encoder coder8_3_1.vhd 8 line/3 line encoder sn7